Bluespec Compiler Design

Synopsys Mentor Cadence TSMC GlobalFoundries SNPS MENT CDNS ( ESNUG 454 Item 2 ) -------------------------------------------- [04/28/06] Subject: ( ) A boatload of users critique Bluespec Design > In one of your recent DAC reports there was a mention of Bluespec System > Verilog, a new behavioral synthesis toolset that promises to 'Reinvent > Hardware Design'. The company, based in Waltham MA, has some fairly > impressive ideas behind its technology, but little in the way validation > in terms of real world industry stories.

Bluespec Joins Synopsys In-Sync Program; Program Participation Enables Bluespec to Verify Interoperability with Synopsys Design Compiler WALTHAM, Mass.--Aug. 15, 2006 --Bluespec Inc., developer of the only ESL synthesis toolset for control logic and complex datapaths in chip design, today announced that it has joined the Synopsys(R) in-Sync(R.

It would be interesting to see > whether there are, among your subscribers, any early adopters or perhaps > even somebody who has taped out a chip using this tool set. What was > their experience using Bluespec? > > - Russ Mestechkin > Analog Devices, Inc.

Norwood, MA From: [ Elvis Lives ] Hi John, Please keep me and our company anonymous. Our company has been evaluating Bluespec for some time now. First there was a 5 day training course before the evaluation period was started. Currently we use Bluespec version 3.8.65 Basically we've been using Bluespec compiler (BSC) to generate RTL Verilog, and then we've simulated the generated design with Modelsim and a VHDL testbench. We haven't been able to compile a Bsim (Bluespec's simulator) executable so far, due to OS reasons, so the support for different Linux/Unix versions could be better. First impressions of the (BSV) language: For each BSV design unit there is a module declaration and an interface declaration.

Usually BSV uses default clocking and reset which are not shown in module declaration. Interface declaration is used to declare methods (and more interfaces) that are used to access the BSV code in the module.

Multi-clock (or reset) designs can be made by adding more clocks (resets )to module definition, not to interface definition. The generated RTL shall have the clocks defined in module declaration and other IO that is defined in interface declaration. Your functionality is described with rules and methods, and for a beginner it is not always clear how rules and methods block each other, especially if the blocking rule is somewhere down in the hierarchy. However after some practice it is possible to write BSV code that will make intented logic and structure in RTL.

Linux tutorial for beginners with examples. A change in thinking is required anyway, since BSV is quite different from VHDL. About BSC compiler: Sometimes the compiler's error messages are cryptic. However with newer version the messages have come a bit more understandable. There are also some switches that allow the compiler to print rule and method scheduling, blocking rule, etc., information of a design. Some swithces are used to control the RTL compilation, too.

For multi clock/reset designs the compiler adds clk_ and rstn_ prefixes to each clock and reset signal, which is a bit annoying. The compiler runs quite fast.

The generated RTL can be compiled and simulated (in Modelsim) and synthesized (Quartus, Precision) without errors. In fact, if there aren't errors in the BSC compilation, your later RTL simulation & synthesis shall work. What would be needed is a better way to simulate BSV code on source code level. The documentation needs to be improved, some things are described very briefly. Bluespec's support for the evaluation has been very good. - [ Elvis Lives ] ---- ---- ---- ---- ---- ---- ---- From: [ Chicken Man ] Hi John, Keep me anonymous. No Bluespec designs yet, but we are planning an eval in the coming months.